1. Field of the Invention
The present invention relates to a method for giving read command to a flash memory and a flash memory controller and a flash memory storage system for using the same.
2. Description of Related Art
Since flash memories are adapted have the characteristics of non-volatile data, power saving, smaller size, and non-mechanical structure, flash memories are suitable for portable appliances, especially portable products powered by batteries. For instance, the solid state drive (SSD) is a storage device using NAND flash memory as a storage medium and is widely used as the major storage device in the notebook computer.
FIG. 1 is a schematic block diagram showing a conventional flash memory storage device. Typically, when the host system 110 is coupled to the flash memory storage device 120 through the connector 122 and is about to read the data stored in the flash memory storage device 120, the procedures for the host system 110 to read the data from the flash memory chip 126 of the flash memory storage device 120 include data uploading, internal data transferring and external data transferring. Specifically, when the host system 110 is about to read the data from the flash memory storage device 120, the flash memory controller 124 gives a general read command to the flash memory chip 126. Meanwhile, the flash memory chip 126 moves the data from the memory cell (i.e. storage region) to the buffer region 132 in the flash memory chip 126 according to the general read command. Thus, the procedure mentioned above is called data uploading. For instance, when the flash memory controller 124 receives a host read command from the host system 110, the flash memory controller 124 gives the flash memory chip 126 a general read command composed of signal streams of “command C1”, “physical address” and “command C2”, wherein the “command C1” is used to instruct the flash memory chip to prepare for executing the read procedure, the “physical address” is used to indicate the address to be read by the flash memory chip and “command C2” is used to instruct the flash memory chip to move the data from the memory cell 134 to the buffer region 132. Meanwhile, the flash memory chip 126 will move the data from the memory cell 134 to the buffer region 132 according to the “physical address” in the general read command.
After finishing the data uploading, the data temporarily stored in the buffer region 132 is transmitted to the flash memory controller 124 (e.g. the buffer memory equipped in the flash memory controller 124). Thus, the procedure mentioned above is called internal data transferring.
Finally, the flash memory controller 124 transmits the received data to the host system 110 through the connector 122. Thus, the procedure mentioned above is called external data transferring.
Particularly, during the data uploading and the internal data transferring, the flash memory chip 126 is at a busy state after the flash memory controller 124 makes the general read command, and, when the flash memory chip 126 is at the busy state, the flash memory controller 124 cannot give any command to the flash memory chip 126. In the other words, the flash memory controller 124 can give the flash memory chip 126 a next command only after the flash memory chip 126 finishes the procedure of data uploading for moving the data from the memory cell 134 to the buffer region 132 and the procedure of internal data transferring for transmitting the data to the flash memory controller 124 from the buffer region 132. For instance, when two consecutive logic addresses (i.e. two pages) are read according to a host read command of the host system 110, it is necessary for the flash memory controller 124 to give the flash memory chip 126 a first general read command composed of the signal streams of “command C1”, “physical address” and “command C2” for performing the data uploading of the data of the first page, and then performing the internal data transferring for transmitting the read data of the first page to the flash memory controller 124, and to give the flash memory chip 124 a second general read command composed of the signal streams of “command C1”, “physical address” and “command C2” for performing the data uploading of the data of the second page, and last performing the internal data transferring for transmitting the read data of the second page to the flash memory controller 124. In the other words, even though the data to be read is stored in the consecutive logic addresses, the flash memory controller 124 needs to repeatedly make the general read commands composed of the signal streams of “command C1”, “physical address” and “command C2” to read the data from the flash memory chip.
With the development of the transmission technology, the transmission speed is greatly improved, such as the transmission speed of the serial advanced technology attachment (SATA) connector is improved to be 15 gigabit per second and even to be 30 gigabit per second. However, the transmission speed of the aforementioned data uploading and the aforementioned internal data transferring is smaller than that of the connector. The entire storage performance cannot be effectively improved. Therefore, it is the goal of the skilled artisan to decrease the time for executing the host read command.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.